A conventional process for manufacturing a magnetic head (for use in mass storage devices such as disk drives and/or tape drives) is illustrated in FIGS. 1A–1H. Specifically, a number of layers (not shown) of a semiconductor wafer are formed in the normal manner, starting with a substrate (not shown) until the three shown in FIG. 1A are formed. Specifically, a first shield layer (not shown) of NiFe (nickel-iron) approximately 2 microns thick is formed over a silicon substrate. This layer is followed a first gap layer and a sensor layer which are both very thin (e.g. 20 nanometers roughly, and <10 nanometers respectively). The first gap layer is typically made of alumina. The sensor is made of layers of combination of metals such as Cu, PtMn, and NiFe. The sensor thickness is about 300 A. Note that the sensor layer forms a read head as discussed below in detail in reference to FIG. 1I.
On top of the sensor layer is a second shield layer formed of NiFe (nickel-iron) approximately 2 microns thick, followed by a second gap layer (e.g. alumina also of 20 nanometers roughly), followed by the three layers shown in FIG. 1A which form a cross-section of a write head along the Y axis. The bottom most layer 101 in FIG. 1A is a NiFe layer which is also 2 microns thick, followed by a gap layer 102 which separates a copper seed layer 103 from the bottom most layer 101. Gap layer 102 is used to insulate two metal layers 101 and 103 from one another, and hence layer 102 is formed of an insulating material (such as alumina) and is sufficiently thick (e.g. 300 nanometers).
After formation of the copper seed layer 103, before formation of the copper layer itself, two photo lithographic steps are performed as follows. A first step is a photolithography and wet chemical etch step which opens row and column boxes and alignment marks for the second step (described later in this paragraph). Note that the row and column boxes and marks are not shown in FIG. 1A because they are in field and dedicated rows which are located far away (in the horizontal direction) from the location of traces and coils (discussed below).
Next, the prior art process defines locations where copper is to be plated. Specifically, copper is plated in regions 104A–104Z (FIG. 1B), but before plating, these regions are covered up with a photoresist (not shown) that is blanket deposited over the entire layer 103 (FIG. 1A), followed by exposure to define regions 104A–104Z. Then, plating is performed to create conductive traces in these regions as shown by coils 105A and trace 105I and coils 105Z in FIG. 1B. Next, a vacuum-based sputter and etch process is performed to remove the copper seed in all regions where copper is not plated, as shown in FIG. 1C. The sputter and etch process is isotropic etch that is performed to remove the seed layer.
Then, a number of via holes (such as via hole 106 in FIG. 1D) are made in the gap layer 102, by first spinning a resist (not shown) on the structure shown in FIG. 1C, followed by exposing the areas to be etched, followed by a chemical wet etch. This process step is followed by removal of the resist (by a resist strip process e.g. using N-methly-pyrrolidone). Next, traces 105A–105Z are protected by formation of a layer 107 of insulation. The insulation layer 107 (not shown) is formed all over the wafer by spinning a resist to fill the space between coils 105A and 105Z, followed by exposure and development. The resist which remains over (and between) coils 105A and 105Z is baked to harden it and make it into permanent insulation 107A and 107B as shown in FIG. 1E. Note that trace 105I forms the write head, and it is left uncovered at this stage, because it needs to be connected later on to a metal via that is yet to be formed.
Next, a full film of nickel iron (NiFe) seed layer 108 is formed all over the wafer as shown in FIG. 1F, followed by spinning a resist which is opened for row and column boxes and alignment marks in the manner described above in reference to FIG. 1A. As noted above, these marks and boxes are in dedicated non-critical areas of the wafer. These marks are used for a photo lithography process similar to FIG. 1C (except that the seed here is NiFe and not Cu). Next step spins a resist followed by openings (not shown) in which are formed vias 109A–109N are by plating NiFe in the openings (at the bottom of which is located seed layer 108). After plating is completed, the seed material in layer 108 that is not located under the vias 109A–109E is removed by sputter/etch process as shown in FIG. 1G. Lastly, an additional insulation layer 110 is formed, of the same material as and in the same manner, as insulation layer 107 (described above). In fact these two layers 107 and 110 are formed of the same insulation material. Thereafter, the wafer is planarized, e.g. by chemical mechanical polishing (CMP) thereby to make it ready for another process.
FIG. 1I illustrates in a perspective view, a magnetic head formed by the process illustrated in FIGS. 1A–1H wherein certain portions form a read head h1 and remaining portions form a write head h2, both heads being laminated on an end surface of a slider 151. Read head hi includes a lower shielding layer 163 made of a magnetic alloy and formed on the end surface of slider 151, and a magnetoresistive element 165 (also called “sensor” in the previous paragraph) is partially exposed at the medium-facing surface. A small magnetic field from the magnetic recording medium when applied to the magnetoresistive element 165 changes a resistance of magnetoresistive element 165 so that a change in voltage based on the change in resistance is read out as a reproduction signal of the magnetic recording medium. Coil 105 which is a part of the write head is patterned to have a spiral planar shape. The write head also includes an upper core layer 178 that is magnetically connected to lower core layer 167 in a central portion of the coil 105.
For more details on the structure of FIG. 1I, see U.S. Pat. No. 6,369,984, which patent is incorporated by reference herein in its entirety. Also incorporated by reference herein in their entirety are the following three U.S. Pat. Nos. 6,154,346, 6,651,312, and 6,452,756 all by Yoshitaka Sasaki.
Applicants note that one or more process steps of the type illustrated in FIGS. 1A–1H are made redundant and one or more layer thicknesses are reduced when two layers are formed in an order inverse of their usage in accordance with the invention as described next.